Dual Core MIPS Instruction Set Processor
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Overview This project was completed for a computer architecture course at Purdue University. VHDL was used to design a dual core, pipelined, MIPS instruction set processor. I completed this project with one other partner. More information can be found in the report below |
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Project Documents Final Report - This is the final report that was written for this project. It contains detailed information about the processor. | ||||
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Pictures
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